Electrical & Computer Engin 667 - Synthesis/Verification DigiSys

Modern techniques for synthesis and verification of digital systems. Topics in synthesis cover high-level synthesis, decision diagrams, multi-level logic and sequential optimization. Topics in verification include symbolic techniques, combinational and sequential equivalence checking, and functional test generation. Open to Graduate Students only. Recommended Prerequisites in the following: "Undergraduate courses in digital logic design and hardware organization"

This course is open to Graduate students in Electrical and Computer Engineering or Electrical Engineering only. Topic Title: Synthesis & Verification of Digital Systems.