Electrical & Computer Engin 597SV - ST-Synthesis/VerificatnDigiSys

Modern techniques for synthesis and verification of digital systems. Topics in synthesis cover high-level synthesis, decision diagrams, multi-level logic and sequential optimization. Topics in verification include symbolic techniques, combinational and sequential equivalence checking, and functional test generation. Recommended prerequisites in the following: undergraduate course in digital logic design.

Open to Seniors and Graduate E&C-ENG majors only. Modern techniques for synthesis and verification of digital systems. Topics in synthesis cover high-level synthesis, decision diagrams, multi-level logic and sequential optimization. Topics in verification include symbolic techniques, combinational and sequential equivalence checking, and functional test generation. Open to graduate and senior undergraduates students. Recommended prerequisites: undergraduate course in digital logic design.