Electrical & Computer Engin 667 - Synthesis/Verification DigiSys

Fall
2020
01
3.00
Maciej Ciesielski
TU TH 10:00AM 11:15AM
UMass Amherst
58654
Fully Remote Class
ciesiel@ecs.umass.edu
58713
Modern techniques for synthesis and verification of digital systems. Topics in synthesis cover high-level synthesis, decision diagrams, multi-level logic and sequential optimization. Topics in verification include symbolic techniques, combinational and sequential equivalence checking, and functional test generation. Recommended prerequisite: undergraduate course in digital logic design.
Graduate EE & CS-ENG students only.
Permission is required for interchange registration during the add/drop period only.
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