Electrical & Computer Engin 567 - Synthesis/VerificatnDigiSys

The course presents a modern approach to logic design and verification of digital circuits. Topics in logic synthesis cover high-level and architectural synthesis, decision and word-level diagrams, combinational and sequential logic optimization. Topics in verification include: simulation-based validation and functional test generation; formal verification techniques; combinational and sequential equivalence checking; and Boolean satisfiability (SAT). Prerequisite: introductory digital circuits; hardware design and organization (undergraduate level). Open to senior undergraduate students.

Open to Seniors and Graduate E&C-ENG majors only. E&C-ENG 124 Modern techniques for synthesis and verification of digital systems. Topics in synthesis cover high-level synthesis, decision diagrams, combinational and sequential logic optimization. Topics in verification include symbolic techniques, equivalence checking, satisfiability, FSM traversal and state reachability analysis. Open to graduate students and senior undergraduate students only. Prerequisites: undergraduate courses in digital logic design and hardware organization.