Electrical & Computer Engin 567 - Synthesis/VerificatnDigiSys

The course presents a modern approach to logic design and verification of digital circuits. Topics in logic synthesis cover high-level and architectural synthesis, decision and word-level diagrams, combinational and sequential logic optimization. Topics in verification include: simulation-based validation and functional test generation; formal verification techniques; combinational and sequential equivalence checking; and Boolean satisfiability (SAT). Prerequisite: introductory digital circuits; hardware design and organization (undergraduate level). Open to senior undergraduate students.

Open to Seniors and Graduate E&C-ENG majors only. E&C-ENG 124 and 331 Prerequisites: E&C-ENG 124, E&C-ENG 331, and E&C-ENG 558/658, or equivalent courses in basic digital logic design, hardware design and organization, and VLSI design (E&C-ENG 558/658 can be taken concurrently).