Electrical & Computer Engin 667 - Synthesis/Verification DigiSys

Modern techniques for synthesis and verification of digital systems. Topics in synthesis cover high-level synthesis, decision diagrams, combinational and sequential logic optimization. Topics in verification include symbolic techniques, equivalence checking, satisfiability, FSM traversal and state reachability analysis. Prerequisites: undergraduate courses in digital logic design and hardware organization.

Graduate EE & CS-ENG students only. Modern techniques for synthesis and verification of digital systems. Topics in synthesis cover high-level synthesis, decision diagrams, combinational and sequential logic optimization. Topics in verification include symbolic techniques, equivalence checking, satisfiability, FSM traversal and state reachability analysis. Open to graduate students and senior undergraduate students only. Prerequisites: undergraduate courses in digital logic design and hardware organization.